MCST-R1000

MCST R1000

File:MCST-4R FPGA prototype.gif MCST R1000 FPGA prototype
General information
Launched	2010 (2010)
Designed by	MCST
Common manufacturer	TSMC
Performance
Max. CPU clock rate	750 MHz to 1 GHz
FSB speeds	2 Gbps
Cache
L1 cache	48 KB
L2 cache	2 MB
Architecture and classification
Application	Embedded
Technology node	100 mm²
Instruction set	SPARC V9
Physical specifications
Cores	4
Package	FPGA
History
Predecessor	MCST-R500S
Successor	MCST-R2000

The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by MCST.

During development this microprocessor was designated as MCST-4R.

MCST R1000 Highlights

• implements the SPARC V9 instruction set architecture (ISA)
• quad-core
• core specifications:
  • in-order, dual-issue superscalar
  • 7-stage integer pipeline
  • 9-stage floating-point pipeline
  • VIS extensions 1 and 2
  • Multiply–accumulate unit
  • 16 KB L1 instruction cache (parity protection)
  • 32 KB L1 data cache (parity protection)
  • size 7.6 mm²
• shared 2MB L2 cache (ECC protection)
• integrated memory controller
• integrated ccNUMA controller
• 1 GHz clock rate
• 90 nm process
• die size 128 mm²
• ~150 million transistors
• power consumption 15W

File:MCST-4R core.gif MCST R1000 core

File:MCST-4R pipeline.gif MCST R1000 pipeline

File:MCST-4R diagram.gif MCST R1000 diagram

File:MCST-4R ccNUMA system.gif ccNUMA multiprocessor system with four MCST R1000 microprocessors