Category:Electronic design automation

C

• Electronic design automation companies (51 P)
• Electronic design automation conferences (6 P)

E

• EDA file formats (15 P)
• Electronic circuit verification (19 P)

H

• Hardware description languages (2 C, 42 P)
• Hardware verification languages (10 P)

I

• IEEE DASC standards (10 P)

N

• Network on a chip (5 P)

O

• Electronics optimization (2 C, 21 P)
• Electronic design automation organizations (1 C, 2 P)

P

• Electronic design automation people (40 P)

S

• Satisfiability modulo theories solvers (3 P)
• Electronic design automation software (4 C, 57 P)

T

• Timing in electronic circuits (1 C, 13 P)

• Electronic design automation

1

• 1-in-3-SAT

A

• AI-driven design automation
• Algorithmic state machine
• And-inverter graph
• Antenna effect
• Asynchronous system

B

• Black's equation
• Boolean satisfiability problem

C

• Cell (EDA)
• Central processing unit
• Chronologic Simulation
• Circuit extraction
• Clock gating
• Correct by Construction

D

• Data processing unit
• Design closure
• Design flow (EDA)
• Design for additive manufacturing
• Design for manufacturability
• Design for testing
• Digital electronics
• Dolphin Semiconductor

E

• EDA database
• Electromagnetic field solver
• Electromigration
• Electronic circuit simulation
• Electronic system-level design and verification
• Elmore delay
• Engineering change order

F

• Fault coverage
• Feedback-controlled electromigration
• Fiduccia–Mattheyses algorithm
• Floorplan (microelectronics)
• FpgaC

G

• Gajski–Kuhn chart
• Generic Array Logic
• Graphical system design
• Graphics processing unit

H

• Handel-C
• Hardware obfuscation
• Hardware watermarking
• High-level synthesis
• High-level verification

I

• IC layout editor
• IEC 61131-3
• Input/output Buffer Information Specification
• Integrated circuit layout

L

• Ladder logic
• Lee algorithm
• List of electrical engineering software
• Logic optimization
• Logic simulation
• Logic synthesis
• Low-power FSM synthesis

M

• Mask data preparation
• Maze runner
• Multi-channel length
• Multi-project wafer service

N

• Netlist
• Network on a chip
• Noise margin

O

• Open Verification Methodology

P

• PBIST
• Physical design (electronics)
• Place and route
• Placement (electronic design automation)
• Planar SAT
• Platform-based design
• Potential applications of carbon nanotubes
• Power gating
• Power network design (IC)
• Power optimization (EDA)
• Programmable Array Logic
• Programmable logic array

R

• Register-transfer level
• Rent's rule
• Resolution enhancement technologies

S

• Satisfiability modulo theories
• SCALD
• Schematic
• Schematic capture
• Schematic editor
• Semiconductor device modeling
• Semiconductor intellectual property core
• Semiconductor process simulation
• Signal integrity
• Signoff (electronic design automation)
• Silicon compiler
• Silvaco Data Systems v. Intel Corp.
• Simulation software
• Standard cell
• Leon Stok
• Stuck-at fault
• Substrate coupling
• Superlog HDL
• Symbolic simulation
• Systems design

T

• Technology CAD
• Test compression
• Touchstone file
• Transaction-level modeling

U

• Ultra-large-scale systems
• Universal Verification Methodology

V

• VISC architecture

X

• XOR-SAT

Y

• Yield (metric)