Category:Computer architecture

• Supercomputers by architecture (3 C, 1 P)
• Operating systems by architecture (6 C, 5 P)

A

• Advanced RISC Computing (19 P)

C

• Capability systems (26 P)
• Central processing unit (6 C, 79 P)
• Classes of computers (42 C, 91 P)
• Computer architects (6 P)
• Computer architecture conferences (3 P)
• Computer arithmetic (5 C, 135 P)
• Computer systems (16 C, 50 P)
• Consistency models (20 P)

D

• Distributed computing architecture (18 C, 101 P)
• Distributed stream processing (5 P)

F

• Fault-tolerant computer systems (6 C, 72 P)
• Flynn's taxonomy (14 P)

H

• Heterogeneous computing (5 C, 9 P)
• High-level language computer architecture (11 P)

I

• IBM PC compatibles (15 C, 154 P)
• Instruction processing (6 C, 69 P)
• Instruction set architectures (14 C, 41 P)
• Interoperability (6 C, 63 P)
• Interrupts (35 P)

M

• Microarchitectures (6 C, 3 P)
• MSX (8 C, 13 P)

N

• Network architecture (14 C, 157 P)
• Network computer (brand) (7 P)

O

• Operating system kernels (7 C, 35 P)
• Operating systems (40 C, 31 P)

R

• Computer hardware researchers (10 P)

S

• Computer architecture statements (29 P)
• Computer data storage (18 C, 49 P)

• Computer architecture

A

• Abstraction layer
• Address space
• Addressing mode
• Aperture (computer memory)
• Approximate computing
• Arithmetic logic unit
• Autonomous decentralized system

B

• Bare machine computing
• Berkeley IRAM project
• Branch Queue
• Bridging model
• Byte addressing

C

• Cache (computing)
• Cache control instruction
• Cache hierarchy
• Cache pollution
• Capability Hardware Enhanced RISC Instructions
• Cellular architecture
• Comparison of CPU microarchitectures
• Comparison of instruction set architectures
• Computational RAM
• Computer architecture simulator
• Computer data storage

D

• Data memory-dependent prefetcher
• Dataflow
• Dataflow architecture
• Directory-based cache coherence
• Directory-based coherence
• Domain-specific architecture
• DOPIPE
• Duncan's taxonomy

E

• Electron E1

F

• Feng's classification
• Frequency scaling

H

• Hardware architect
• Hardware-assisted garbage collection
• Harvard architecture
• Hybrid-core computing

I

• IBM System/360 architecture
• Instruction prefetch
• Instruction window

L

• Load–store architecture
• Load–store unit

M

• The Machine (computer architecture)
• Machine Check Architecture
• Manycore processor
• MCDRAM
• Memory dependence prediction
• Memory disambiguation
• Memory hierarchy
• Memory management
• Memory ordering
• Microarchitecture simulation
• Modified Harvard architecture
• Multi-core processor

N

• Network Centric Product Support
• NonStop (server computers)
• Northbound interface

O

• Open architecture

P

• Popek and Goldberg virtualization requirements
• Processor register

R

• Random-access memory
• Reference model
• Register file
• Register renaming
• Register–memory architecture
• Resilience (network)
• Responsiveness

S

• Scalability
• Scale cube
• Shared memory
• Sierpiński graph
• Simple-As-Possible computer
• Simultaneous multithreading
• Single instruction, multiple threads
• Single-core
• Slot (computer architecture)
• Spatial architecture
• SpiNNaker
• Stream processing
• Superscalar processor
• Synchronous Data Flow

T

• Tagged architecture
• Temporal multithreading
• Transport triggered architecture

U

• Unix architecture

V

• Vectored interrupt
• Vkernel
• Von Neumann architecture

W

• Whitewater Interactive System Development with Object Models

X

• Xputer