Category:Central processing unit

• Central processing unit
• VISC architecture

A

• Accumulator (computing)
• Address generation unit
• Architectural state
• Arithmetic logic unit
• Autonomous peripheral operation

B

• Barrel processor
• Berkeley RISC
• Bit slicing
• Byte addressing

C

• Computer architecture
• Computer for operations with functions
• Control register
• Control unit
• Computer cooling
• Coprocessor
• CPU cache
• CPU card
• CPU core voltage
• CPU modes
• Cycle stealing

D

• Datapath
• Delay insensitive circuit
• Dirty bit
• Double fault
• Dynamic frequency scaling

E

• Execute instruction
• Execution unit

F

• Flag (programming)
• Floating-point unit
• Frequency scaling

H

• Hardware acceleration
• Hardware performance counter
• Hardware register
• Hardware reset
• History of general-purpose CPUs

I

• Index register
• Instruction set architecture
• Instruction unit

M

• Media processor
• Memory management unit
• Memory protection unit
• Micro-operation
• Microarchitecture
• Microcode
• Microsequencer
• Millicode
• Minimal instruction set computer
• Multithreading (computer architecture)

N

• No instruction set computing
• NX bit

P

• Page (computer memory)
• Parity flag
• Processor design
• Processor power dissipation
• Processor register
• Processor supplementary capability
• Program counter

R

• Register window
• Rekursiv
• Repeat instruction
• Reset vector
• Protection ring

S

• Scalar processor
• Simultaneous multithreading
• Stack register
• Static core
• Program status word
• Status register
• Stepping level

T

• Temporal multithreading
• Tile processor
• Translation lookaside buffer
• Trap flag
• TRIPS architecture

V

• Vector processor

W

• Wait state

Z

• Zero instruction set computer