Template:X86 protected mode interrupts

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x86 Interrupt descriptor table items[1] [edit table]
Int. № Mnem. Type Err. code[a] Name Source
hex dec
0x00 0 #DE Fault[b] No Divide Error Integer divide instructions: DIV, IDIV and AAM.
0x01 1 #DB Trap/Fault[c] No Debug Exception Instruction, data, and I/O breakpoints; single-step; INT1/ICEBP instruction and others.
0x02 2 NMI[d] Interrupt No NMI Interrupt Nonmaskable external interrupt.
0x03 3 #BP Trap No Breakpoint INT3 instruction.
0x04 4 #OF Trap No Overflow INTO instruction.
0x05 5 #BR Fault[b] No BOUND Range Exceeded BOUND instruction. Can also be generated by the Intel MPX instructions BNDCL,BNDCU,BNDCN,BNDLDX and BNDSTX.
0x06 6 #UD Fault No Invalid Opcode (Undefined Opcode) UD instruction or reserved opcode.
0x07 7 #NM Fault No Device Not Available (No Math Coprocessor)
  • Any x87 instruction when CR0.EM is set.
  • WAIT/FWAIT instruction when both CR0.TS and CR0.MP are set.
  • Any x87 or SIMD (MMX/SSE/AVX/AVX-512/AMX) instruction when CR0.TS is set.
0x08 8 #DF Abort Yes (zero) Double Fault Any instruction that can generate an exception, an NMI, or an INTR.
0x09 9 #MP[e] Abort No Coprocessor Segment Overrun

(reserved on 486 and later)

x87 floating-point instruction with a memory operand when middle part of memory operand is in inaccessible memory.[3][4]

(80287/80387 only; Intel 80486 and later processors will instead generate #GP or #PF exceptions for such operands)

0x0A 10 #TS Fault Yes Invalid TSS Task switch or TSS access.
0x0B 11 #NP Fault Yes Segment Not Present Loading segment registers or accessing system segments.
0x0C 12 #SS Fault Yes Stack-Segment Fault Stack operations and SS register loads.
0x0D 13 #GP Fault Yes General Protection Any memory reference and other protection checks.
0x0E 14 #PF Fault Yes Page Fault Any memory reference.
0x0F 15 — Intel reserved. Do not use.
0x10 16 #MF Fault No x87 FPU Floating-Point Error (Math Fault) x87 FPU floating-point, WAIT/FWAIT or MMX instruction.[f]
0x11 17 #AC Fault Yes Alignment Check Misaligned memory access.

On some newer processors, #AC can also be generated by instructions that try to perform locked accesses on uncacheable memory.

0x12 18 #MC Abort/
Fault/
Interrupt[g] 		No Machine Check Hardware error.

Error information is provided by machine-check MSRs. The set of errors that can be detected and reported through the Machine Check mechanism, as well as the MSRs that can hold the error information, are processor model dependent.

0x13 19 #XM Fault No SIMD Floating-Point Exception SSE/SSE2/SSE3/AVX/AVX2/AVX-512 floating-point instructions.
0x14 20 #VE Fault No Virtualization Exception EPT (Extended Page Table) violations (Intel VT-x guest only)
0x15 21 #CP Fault Yes Control Protection Exception When CET shadow stacks are enabled, the RET, IRET, RSTORSSP, and SETSSBSY instructions can generate this exception.

When CET indirect branch tracking is enabled, this exception can be generated due to a missing ENDBRANCH instruction at the target of an indirect call or jump.

0x16
⋮
0x1B 		22
⋮
27 		— Reserved for future use as CPU exception vectors.
0x1C 28 #HV Interrupt No Hypervisor Injection Exception Event injection from hypervisor to SNP guest (AMD SEV-SNP guest only)
0x1D 29 #VC Fault Yes VMM Communication Exception Virtual-machine exit events that require the VMM to inspect guest register state (AMD SEV-ES guest only)
0x1E 30 #SX Interrupt Yes Security Exception Security-sensitive event (AMD SVM VMM only)
0x1F 31 — Reserved for future use as CPU exception vector.
0x20
⋮
0xFF 		32
⋮
255 		— Interrupt No — External interrupts.
  1. ^ This column determines whether the interrupt pushes an exception code to the interrupt handler stack, or not. For some exceptions, this pushes only a zero number
  2. ^ a b The #DE (divide error) and #BR (bound range exceeded) are fault-type exceptions on 80286 and later processors; on earlier processors, they were traps.
  3. ^ The #DB exception may be either a trap or a fault exception depending on the condition that caused the exception. (E.g. instruction breakpoints are faults, while data breakpoints and single-steps are traps.) The condition that caused the #DB exception can be identified by inspecting the DR6 debug register.
  4. ^ The official Intel documentation does not assign an official mnemonic to this interrupt, but abbreviation “NMI” is widely used to refer to this interrupt, even in the Intel docs itself.
  5. ^ The #MP mnemonic for exception 9 is listed in Intel 80286 documentation only[2] − later Intel documentation for 80386 and later processors continues to describe this exception but no longer uses the #MP mnemonic for it.
  6. ^ When an unmasked math exception is detected in the x87 FPU, it is not signalled as a fault on the x87 instruction producing the exception, but instead on the next x87/FWAIT/MMX instruction.
  7. ^ On x86 processors that support Machine Check Architecture (Intel Pentium Pro and later, AMD K7 and later), the #MC exception may act as either an Abort, Fault or Interrupt type exception depending on the type of error that caused the exception. This is indicated with the RIPV bit (bit 0) and EIPV bit (bit 1) of the MCG_STATUS MSR (MSR 17Ah):
    • The RIPV bit indicates whether the instruction stream can be restarted from the CS:rIP value pushed on the stack (1=yes, 0=no)
    • The EIPV bit indicates whether the error is associated with the instruction pointed to by the CS:rIP value pushed on the stack (1=yes, 0=no)
  1. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  2. ^ Intel, iAPX 286 Programmer's Reference Manual, order no. 210498-001, 1983, appendix B, table B-2, page 202.
  3. ^ Intel, 80387 Programmer's Reference Manual, order no. 231917-001, 26 May 1987, table 2.6 on page 211.
  4. ^ Intel, 80286 and 80287 Programmer's Reference Manual, order no. 210498-005, section 9.6.3 on page 172.
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