Template
:
Hardware acceleration
From Wikipedia, the free encyclopedia
Jump to navigation
Jump to search
v
t
e
Hardware acceleration
Theory
Universal Turing machine
Parallel computing
Distributed computing
Applications
GPU
GPGPU software
DirectX
Audio
Digital signal processing
Hardware random number generation
Neural processing unit
Cryptography
TLS
Machine vision
Custom hardware attack
scrypt
Networking
Data
Implementations
High-level synthesis
C to HDL
FPGA
ASIC
CPLD
System on a chip
Network on a chip
Architectures
Dataflow
Transport triggered
Multicore
Manycore
Heterogeneous
In-memory computing
Systolic array
Neuromorphic
Related
Programmable logic
Processor
design
chronology
Digital electronics
Virtualization
Hardware emulation
Logic synthesis
Embedded systems
Template documentation
[
create
] [
purge
]
Editors can experiment in this template's sandbox
(
create
|
mirror
)
and testcases
(
create
)
pages.
Add categories to the
/doc
subpage.
Subpages of this template
.
Category
:
Computer hardware navigational boxes
Navigation menu
Personal tools
Not logged in
Talk
Contributions
Create account
Log in
Namespaces
Template
Talk
English
Views
Read
Edit source
View history
More
Search
Navigation
Main page
Contents
Current events
Random article
About Wikipedia
Contact us
sitesupport
Contribute
Help
Learn to edit
Community portal
Recent changes
Upload file
Special pages
Tools
What links here
Related changes
Printable version
Permanent link
Page information