Server Base System Architecture
The Server Base System Architecture (SBSA) is a hardware system architecture for servers based on 64-bit ARM processors.[1][2][3][4]
Rationale
[edit | edit source]Historically, ARM-based products have often been tailored for specific applications and power profiles. Variation between ARM-based hardware platforms has been an impediment requiring operating system adjustments for each product.
The SBSA seeks to strengthen the ARM ecosystem by specifying a minimal set of standardized features so that an OS built for this standard platform should function correctly without modification on all hardware products compliant with the specification.
Features
[edit | edit source]- CPU features
- Memory management
- Peripheral access
- Interrupts
- Watchdog (errant system detection)
Existing specifications for USB, PCIe, ACPI, TPM, and other standards are incorporated to solidify the specification.
Server Base Boot Requirements
[edit | edit source]Firmware issues are addressed separately in the Server Base Boot Requirements (SBBR) specification.[5]
Platform validation
[edit | edit source]The Architecture Compliance Suite (ACS) checks whether an environment is compliant with the SBSA specification, and is provided under an Apache 2 open source license. It is available at https://github.com/ARM-software/sbsa-acs.
Compliance levels
[edit | edit source]The specification defines levels of compliance, with level 0 being the most basic, and successive levels building on prior levels. In the words of the spec, "Unless explicitly stated, all specification items belonging to level N apply to levels greater than N."
Level 0, 1, and 2
[edit | edit source]Levels 0, 1, and 2 have been deprecated and folded into level 3.
Level 3
[edit | edit source]Level 3 contains base-level specifications for:
- PE (Processing Element--a core) features
- Memory map
- Interrupt controller
- PPI (peripheral interrupt) assignments
- MMU behavior
- Clock and timer subsystem
- Wake up semantics
- Power state semantics
- Watchdogs
- Peripheral subsystems
Level 4
[edit | edit source]Extends level 3, e.g. with support for RAS fault recovery extensions of ARMv8.2 spec.
Level 5
[edit | edit source]Extends level 4, e.g. with support for stage 2 translation control from hypervisor as specified in ARMv8.4.
Level 6
[edit | edit source]Extends level 5, e.g. with support for speculative execution safety features.
Level 7
[edit | edit source]Extends level 6, e.g. with support for Arm Memory System Resource Partitioning and Monitoring (MPAM) and Performance Monitoring Unit (PMU) features.
Versions
[edit | edit source]Initial public version
[edit | edit source]Initial public version of the SBSA was announced on January 29, 2014.
SBSA Version 3.0
[edit | edit source]SBSA Version 3.0 was released on February 1, 2016.
SBSA Version 5.0
[edit | edit source]SBSA Version 5.0 was released on May 30, 2018.
SBSA Version 6.0
[edit | edit source]SBSA Version 6.0 was released on September 16, 2019.
SBSA Version 6.1
[edit | edit source]SBSA Version 6.1 was released on September 15, 2020.
SBSA Version 7.0
[edit | edit source]SBSA Version 7.0 was released on January 31, 2021.
SBSA Version 7.1
[edit | edit source]SBSA Version 7.1 was released on October 6, 2022.
See also
[edit | edit source]References
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