Draft:Nano-ridge engineering

From Wikipedia, the free encyclopedia
Jump to navigation Jump to search
  • Comment: This is an advert for a product of imec. We do not accept adverts. Ldm1954 (talk) 13:24, 14 December 2025 (UTC)

Nano-ridge engineering (NRE) is a monolithic integration method that allows for the direct deposition of high crystal quality III-V semiconductors on Silicon (Si) substrates with high aspect ratio ratio trench patterns. This approach holds the potential to enable cost-effective, scalable integration of III–V devices with existing silicon-based technologies, unlocking new opportunities in high-speed electronics, sensing, and silicon photonics.

Background

[edit | edit source]

Ever since the invention of the transistor in 1947, the microelectronics industry has been dominated by group IV semiconductor devices, owing to the success of Si complementary metal oxide semiconductor (CMOS).[1].The Si industry has reached high levels of sophistication, with advanced and mature processes enabling the production of high-performance, cost-effective devices at an unprecedented scale. This maturity, coupled with the unlimited availability of Si, has cemented Si's position as the dominant material in both the logic and memory industries.

However, Si cannot fulfil all the demands of modern electronics, particularly in the realm of optoelectronics. Compound materials, such as III-V semiconductors, possess intrinsic properties that make them better suited for applications involving light emission/detection and high-frequency operation. III-V materials excel in areas like photonic devices (LEDs, lasers, ...), imaging/sensing and high-speed transistors such as high-electron-mobility transistors (HEMT) and heterojunction bipolar transistors (HBT) where Si falls short due to its indirect bandgap and lower electron mobility. In particular, the increasing demand for connectivity in our society requires advanced wireless and optoelectronic data communications supported by III-V based functionalities [2]. As a result, significant research efforts have been directed toward integrating III-V materials with Si substrates, with the aim of combining the optoelectronic capabilities of III-V semiconductors with the scalability, cost-efficiency, and process advancements of the Si industry [3][4][5]. Different integration approaches are being explored to realize this feat, with the heterogeneous integration of III-V layers or devices to Si-based functionalities being the most mature one. On the other hand, the monolithic integration, defined as the direct growth of III-V materials on Si substrates, offers the highest-level of economic viability and integration density [6].

The primary challenge in directly depositing III-V materials onto Silicon lies in the formation of crystallographic defects caused by the lattice mismatch between Si and most III-V material systems [7]. Nano-ridge engineering (NRE), introduced by imec, offers a potential solution to this fundamental issue, allowing for the monolithic integration of high quality III-V materials onto large-diameter Si wafer (electronics)[8][9][10][11]. This approach bears the opportunity of being cost-effective, CMOS-compatible and sustainable, making it a promising integration concept with potential for widespread adoption.

Concept

[edit | edit source]
Scanning electron microscope images of GaAs nano-ridges deposited on 300 mm trench-patterned Si substrate. The images were taken from different mask locations to show the impact of the pitch and trench size[8].

The concept of NRE is based on the selective area growth of III-V materials using metalorganic vapour-phase epitaxy (MOVPE) within narrow trenches patterned on a large-diameter, (001) exactly oriented Si wafer. By designing trenches with a high aspect ratio —defined as the ratio of trench height to width—the efficient trapping of relaxation defects can be achieved, a mechanism known as aspect ratio trapping (ART) [12].

a) Sketch of threading dislocation half-loops being trapped at the oxide side walls. b) Scanning electron microscope images of GaAs nano-ridges in cross-section indicating the position of the transmission electron microscope lamella shown in c). Annular bright-field scanning transmission electron microscope image along a GaAs nano-ridge revealing efficient trapping of threading dislocations (TD)[8].

The application of a V-shape Si surface exposing two {111} facets enhances the strain relaxation along the III-V/Si interface and prevents the formation of III-V anti-phase domains. Once the trenches are filled, the III-V growth extends beyond the patterned trenches, forming large III-V nano-ridges with increased material volume and low defect density. This ability to control the shape of the nano-ridges through careful tuning of MOVPE deposition parameters is what gives NRE its name. The increased III-V nano-ridge volume opens up possibilities for novel device architectures and applications, ranging from nano-ridge lasers and detectors for silicon photonics [13][14][15] up to HBTs in radio frequency (RF) technologies [16][17]. In particular, for Si-based photonic integrated circuits (PICs), integrating III-V nano-ridges as waveguides containing an active laser medium could enable new circuit designs for on-chip interconnects [18].

a) to d) are scanning electron microscope (SEM) images of GaAs nano-ridges, which were deposited under different MOVPE growth conditions. Due to the different surface properties of the nano-ridge facets (classified by the Miller indices), a change in deposition conditions, such as substrate temperature, III-V growth rate, V/III gas ratio etc., leads to a change in the growth rate hierarchy on the diverse nano-ridge facets. The growth rate hierarchy defines the final shape of the nano-ridge while the facets with the lowest growth rate dominate the final shape. The sketches next to the SEM images indicate with the red arrow size, which growth rate dominated the hierarchy to achieve the corresponding GaAs nano-ridge shape[8]. Similar observations have been previously reported. If the growth rate is known, a prediction of the nano-ridge shape is possible via a Wulff Construction.

One of the milestones demonstrating the potential of this approach is the fabrication of III-V nano-ridge lasers on 300 mm Si substrates, processed entirely within a CMOS prototyping line at imec [19]. In addition, the CMOS-compatible processing of GaAs- and InP-based HBTs was also demonstrated [20]. These efforts highlight the promise of NRE as a scalable and cost-effective monolithic integration technique. By eliminating the need for III-V substrates and relying on selective area epitaxy to minimize III-V material usage, this method also offers a sustainable solution from a resource-efficiency perspective.

However, despite its potential, considerable research is required before NRE-based devices can be brought to market. Handling III-V materials in a CMOS manufacturing environment is still uncommon, and specialised III-V processing tools are not yet widely available. In addition, the novel nano-ridge device designs require adaptations to the overall circuit architectures. Thus, while NRE-based III-V device integration represents a long-term solution with the potential to transform connectivity, photonics and sensing, further development is essential to unlock its full potential.

a) to c) are scanning electron microscope (SEM) images of III-V nano-ridges in cross-section, which were deposited under different MOVPE conditions. The results in a) refer to [21],b) to [11] and c) to [22]

References

[edit | edit source]
  1. ^ Brinkman, W. F., Haggan, D. E., & Troutman, W. W. (1997)
  2. ^ Hecht, J. (2016). The bandwidth bottleneck. Nature, 536(7615), 139-142
  3. ^ https://irds.ieee.org/images/files/pdf/2022/2022IRDS_WP-MtM.pdf [bare URL PDF]
  4. ^ https://www.imec-int.com/en/articles/scaling-gan-and-inp-based-technologies-5g-and-6g-wireless-communication
  5. ^ Liang, D., & Bowers, J. E. (2021). Recent progress in heterogeneous III-V-on-silicon photonic integration. Light: Advanced Manufacturing, 2(1), 59-83.
  6. ^ Van Thourhout, D., Wang, Z., & Roelkens, G. (2017). III-V on silicon integration. Optics & Photonics News, 34-39.
  7. ^ Kunert, B., Mols, Y., ²Baryshniskova, M., Waldron, N., Schulze, A., & Langer, R. (2018). How to control defect formation in monolithic III/V hetero-epitaxy on (100) Si? A critical review on current approaches. Semiconductor Science and Technology, 33(9), 093002.
  8. ^ a b c d https://compoundsemiconductor.net/article/104936/Gaining_an_edge_with_nano-ridges
  9. ^ Kunert, B., Guo, W., Mols, Y., Langer, R., & Barla, K. (2016). Integration of III/V hetero-structures by selective area growth on Si for nano-and optoelectronics. Ecs Transactions, 75(8), 409.
  10. ^ Van Thourhout, D., Shi, Y., Baryshnikova, M., Mols, Y., Kuznetsova, N., De Koninck, Y., ... & Kunert, B. (2019). Nano-ridge laser monolithically grown on (001) Si. In Semiconductors and Semimetals (Vol. 101, pp. 283-304). Elsevier.
  11. ^ a b Baryshnikova, M., Mols, Y., Ishii, Y., Alcotte, R., Han, H., Hantschel, T., ... & Kunert, B. (2020). Nano-ridge engineering of GaSb for the integration of InAs/GaSb heterostructures on 300 mm (001) Si. Crystals, 10(4), 330.
  12. ^ Fiorenza, J. G., Park, J. S., Hydrick, J., Li, J., Li, J., Curtin, M., ... & Lochtefeld, A. (2010). Aspect ratio trapping: a unique technology for integrating Ge and III-Vs with silicon CMOS. ECS Transactions, 33(6), 963.
  13. ^ Shi, Y., Pantouvaki, M., Van Campenhout, J., Colucci, D., Baryshnikova, M., Kunert, B., & Van Thourhout, D. (2021). Loss-coupled DFB nano-ridge laser monolithically grown on a standard 300-mm Si wafer. Optics Express, 29(10), 14649-14657.
  14. ^ Colucci, D., Baryshnikova, M., Shi, Y., Mols, Y., Muneeb, M., Koninck, Y. D., ... & Kunert, B. (2022). Unique design approach to realize an O-band laser monolithically integrated on 300 mm Si substrate by nano-ridge engineering. Optics Express, 30(8), 13510-13521.
  15. ^ Ozdemir, C. I., De Koninck, Y., Yudistira, D., Kuznetsova, N., Baryshnikova, M., Van Thourhout, D., ... & Van Campenhout, J. (2021). Low dark current and high responsivity 1020nm InGaAs/GaAs nano-ridge waveguide photodetector monolithically integrated on a 300-mm Si wafer. Journal of Lightwave Technology, 39(16), 5263-5269.
  16. ^ Vais, A., Witters, L., Mols, Y., Hernandez, A. S., Walke, A., Yu, H., ... & Collaert, N. (2019, December). First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering. In 2019 IEEE International Electron Devices Meeting (IEDM) (pp. 9-1). IEEE.
  17. ^ Mols, Y., Vais, A., Yadav, S., Witters, L., Vondkar, K., Alcotte, R., ... & Kunert, B. (2021). Monolithic integration of nano-ridge engineered InGaP/GaAs HBTs on 300 mm Si substrate. Materials, 14(19), 5682.
  18. ^ Shi, Y., Kunert, B., De Koninck, Y., Pantouvaki, M., Van Campenhout, J., & Van Thourhout, D. (2019). Novel adiabatic coupler for III-V nano-ridge laser grown on a Si photonics platform. Optics express, 27(26), 37781-37794.
  19. ^ De Koninck, Y., Caer, C., Yudistira, D., Baryshnikova, M., Sar, H., Hsieh, P. Y., ... & Van Campenhout, J. (2025). GaAs nano-ridge laser diodes fully fabricated in a 300-mm cmos pilot line. Nature, 637(8044), 63-69.
  20. ^ Vais, A., Kumar, A., Boccardi, G., Yadav, S., Mols, Y., Alcotte, R., ... & Collaert, N. (2024). A CMOS Compatible III-V-on-300 mm Si Technology for Future High-speed Communication Systems: Challenges and Possibilities. Key Enabling Technologies for Future Wireless, Wired, Optical and Satcom Applications, 27.
  21. ^ Kunert, B., Alcotte, R., Mols, Y., Baryshnikova, M., Waldron, N., Collaert, N., & Langer, R. (2021). Application of an sb surfactant in InGaAs nano-ridge engineering on 300 mm silicon substrates. Crystal Growth & Design, 21(3), 1657-1665.
  22. ^ Mols, Y., Bogdanowicz, J., Favia, P., Lagrain, P., Guo, W., Bender, H., & Kunert, B. (2019). Structural analysis and resistivity measurements of InAs and GaSb fins on 300 mm Si for vertical (T) FET. Journal of Applied Physics, 125(24).
Retrieved from "http://70.231.62.181/index.php?title=Draft:Nano-ridge_engineering&oldid=25430555"