Delta delay

From Wikipedia, the free encyclopedia
Jump to navigation Jump to search

In VHDL simulations, all assignments to signals (a VHDL concept that represents a net connecting different components together) occur with some infinitesimal delay, known as delta delay, unless a delay is specified.[1] Technically, delta delay is of no measurable unit, but from a digital electronics hardware design perspective one should think of delta delay as being the smallest time unit one could measure, such as a femtosecond (fs).

References

[edit | edit source]
  1. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).