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{{Short description|Software for high-performance networking}}
{{Infobox software
| name = Portals
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| developer = [[Sandia National Laboratories]], [[University of New Mexico]]
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| latest release version = 4.0.2{{When|date=October 2014}}
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| genre = Network [[Application programming interface|API]]
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| website = {{URL|http://www.sandia.gov/Portals}}
}}
'''Portals''' is a low-level network [[Application programming interface|API]] for high-performance networking on [[high-performance computing]] systems developed by [[Sandia National Laboratories]] and the [[University of New Mexico]]. Portals is currently the lowest-level network programming interface on the commercially successful XT line of supercomputers from [[Cray]].

== Overview ==
Portals is based on the concept of elementary building blocks that can be combined to support a wide variety of upper-level network transport semantics. Portals provides one-sided data movement operations, but unlike other one-sided programming interfaces, the target of a remote operation is not a [[virtual address]]. Instead, the ultimate destination in memory of an incoming message is determined at the receiver by comparing contents of the message header with the contents of structures at the destination. This flexibility allows for efficient implementations of both one-sided and two-sided communications. In particular, Portals is aimed at providing the fundamental operations necessary to support a high-performance and scalable implementation of the [[Message Passing Interface]] (MPI) standard.<ref name=brightwell-1996 /> It was also used as the initial network transport layer for the [[Lustre (file system)|Lustre]] file system.

== Early years ==
Portals began in the early 1990s as an extension to the [[NCUBE|nX]] message passing system used in the [[SUNMOS]] and [[PUMA Cluster Super Computer|Puma]] operating system. It was first implemented for the [[Intel Paragon]] at Sandia, and later ported to the [[Intel Teraflops|Intel TeraFLOPS]] machine named [[ASCI Red]].<ref name=brightwell-1996>{{cite conference
| citeseerx = 10.1.1.54.3830
| title = Design and Implementation of MPI on Puma Portals
| author = Ron Brightwell| date = June 1996
| conference = MPI Developer's Conference, 1996. Proceedings., Second
|display-authors=etal}}</ref>
There were four building blocks in the first version of Portals: the single block, the dynamic block, the independent block and the combined block. All incoming messages would first pass through a match-list that allowed individual portals to respond to specific groups, ranks, and a set of user specified match-bits.<ref name=brightwell-1996 />

== Portals 3 ==
The Portals concept continued to evolve over successive generations of lightweight kernels and massively parallel systems. In 1999, an operational programming interface was given to Portals so that it could be implemented for intelligent or programmable network interfaces outside of a lightweight kernel environment.<ref name="portals3.0">{{cite report
| author = Ron Brightwell 
| title = The Portals 3.0 Message Passing Interface Revision 1.0
| institution = Sandia National Laboratories
| location = Albuquerque, NM
| date = December 1999
| url = https://www.sandia.gov/app/uploads/sites/144/2021/11/portals30.pdf
| format = PDF
| display-authors= etal
}}</ref> This standard was designed for systems where the work required to prepare, transmit, and deliver messages is longer than the round-trip to the Portals data structures. For example, in modern systems, this work is dominated by the round-trip through the IO bus to the network interface. The standard has been revised since the initial release to make it more suited for modern high performance, massively parallel computers.<ref name="portals3.3">{{cite report
| author = Rolf Riesen 
| title = The Portals 3.3 Message Passing Interface Document Revision 2.1
| institution = Sandia National Laboratories
| location = Albuquerque, NM
| date = April 2006
| url = https://www.sandia.gov/app/uploads/sites/144/2021/11/portals33.pdf
| format = PDF
| archive-url = https://web.archive.org/web/20110605103014/http://www.cs.sandia.gov/Portals/publications/portals33.pdf
| archive-date = 2011-06-05
| url-status = dead
| access-date = 2009-10-02
| display-authors= etal
}}</ref>
The MPI library was ported from the [[retronym]]ed Portals 2 to the new Portals 3.0.<ref name=brightwell-2002>{{cite book
| title = Design and Implementation of MPI on Portals 3.0
| series = Lecture Notes in Computer Science
| publisher = Springer
| year = 2002
}}</ref>

The Portals 3 specification has been implemented several times, first on [[ASCI Red]], then on [[CPlant]] over [[Myrinet]],<ref name=pundit-2001>{{cite journal
| url = http://www.ieeetcsc.org/node/37/634
| title = CPlant: The Largest Linux Cluster
| author = Neil Pundit
| publisher = IEEE Technical Committee on Scalable Computing
| accessdate = 2009-10-02
}}</ref> [[Linux]] and the [[Cray XT3|Cray XT]] family.<ref name="pedretti-2005">{{cite conference
| author = Kevin Pedretti 
| title = Implementation and Performance of Portals 3.3 on the Cray XT3
| conference = IEEE International Conference on Cluster Computing
| location = Boston, MA
| date = 2005-09-27
| publisher = IEEE Computer Society
| pages = 1–8
| display-authors= etal
}}</ref>

== Portals 4 ==
In light of emerging [[partitioned global address space]] (PGAS) languages, several new features have been added to the Portals API as part of Portals 4. Portals 4 also made several changes to improve the interaction between the processor and network interface (NIC) for implementations that provide offload. Finally, an option to support a form of flow-control was added to Portals 4.<ref name="portals4.0">{{cite report
| author = Ryan Grant 
| title = The Portals 4.0.2 Message Passing Interface
| institution = Sandia National Laboratories
| location = Albuquerque, NM
| date = 2014-10-01
| url = https://www.sandia.gov/app/uploads/sites/144/2021/11/portals402.pdf
| format = PDF
| access-date = 2016-03-25
| display-authors= etal
}}</ref>

Portals 4 is the low-level networking API for the Bull-Atos BXI NIC.<ref>{{cite conference
| last1 = Derradji | first1 = S.
| last2 = Palfer-Sollier | first2 = T.
| last3 = Panziera | first3 = J.P.
| last4 = Poudes | first4 = A.
| last5 = Wellenreiter | first5 = F.
| title = The BXI Interconnect Architecture
| book-title = Symposium on Hot Interconnects
| publisher = IEEE
| date = August 26, 2015
| doi = 10.1109/HOTI.2015.15
}}</ref>

== External links ==
* [http://www.cs.sandia.gov/Portals Portals Home Page]

== References ==
{{reflist}}

[[Category:Application programming interfaces]]
[[Category:Parallel computing]]

Portals network programming application programming interface - Revision history

imported>LucasBrown: WP:SDCONTENT compliance