Zen 5

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Zen 5
File:AMD Ryzen 9 9950X.jpg
AMD Ryzen 9 9950X
General information
LaunchedMobile
July 17, 2024; 20 months ago (2024-07-17)

Desktop
August 8, 2024; 20 months ago (2024-08-08)

High-end Desktop
August 30, 2025; 7 months ago (2025-08-30)

Server
October 10, 2024; 18 months ago (2024-10-10)
Designed byAMD
Common manufacturer
CPUID codeFamily 1Ah
Cache
L1 cache80 KB (per core):
  • 32 KB instructions
  • 48 KB data
L2 cache1 MB (per core)
L3 cache
  • 32–128 MB (32 MB per CCD + 64 MB with 3D V-cache)
  • 24 MB (in Strix Point)
Architecture and classification
Technology nodeTSMC N4X (Zen 5 CCD)
TSMC N3E (Zen 5c CCD)
TSMC N6 (IOD)
TSMC N4P (Mobile)
MicroarchitectureZen
Instruction setAMD64 (x86-64)
Extensions
Physical specifications
Cores
  • Mobile: 8 to 12
    Desktop: 6 to 16
    Server: 16 to 192
Memory (RAM)
Package
  • FP8, FL1
Sockets
Products, models, variants
Product code names
  • Core
    • Nirvana (Zen 5)
    • Prometheus (Zen 5c)
  • Desktop
    • Granite Ridge
  • HEDT/Workstation
    • Shimada Peak
  • Thin & Light Mobile
    • Strix Point
    • Krackan Point
  • Extreme Mobile
    • Strix Halo
    • Fire Range
  • Server
    • Turin
    • Turin Dense
Brand names
History
PredecessorZen 4 • Zen 4c
SuccessorZen 6 • Zen 6c
File:AMD Zen5台式机评测：积热大幅改善？ (2160p 60fps VP9-160kbit Opus)-00.00.18.800.png
Two AMD Ryzen 9000 series microprocessors with Zen 5 architecture

Zen 5 ("Nirvana")[1] is a CPU microarchitecture by AMD, shown on their roadmap in May 2022,[2] launched for mobile in July 2024 and for desktop in August 2024.[3] It is the successor to Zen 4 and is currently fabricated on TSMC's N4P process.[4] Zen 5 is also planned to be fabricated on the N3E process in the future.[5]

The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server processors (codenamed "Turin"),[6] and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").[7][8]

Background

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Zen 5 was first officially mentioned during AMD's Ryzen Processors: One Year Later presentation on April 9, 2018.[9]

A roadmap shown during AMD's Financial Analyst Day on June 9, 2022 confirmed that Zen 5 and Zen 5c would be launching in 3 nm and 4 nm variants in 2024.[10] The earliest details on the Zen 5 architecture promised a "re-pipelined front end and wide issue" with "integrated AI and Machine Learning optimizations".

During AMD's Q4 2023 earnings call on January 30, 2024, AMD CEO Lisa Su stated that Zen 5 products would be "coming in the second half of the year".[11]

Architecture

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Die-Shot of an AMD Ryzen 5 9600X, mainly in blue, and rather symmetric structure
Die-Shot of an AMD Ryzen 5 9600X with a Zen 5 microarchitecture

Zen 5 is a ground-up redesign of Zen 4 with a wider front-end, increased floating-point throughput, and more-accurate branch prediction.[12]

Fabrication process

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Zen 5 was designed with both 4 nm and 3 nm processes in mind. This acted as an insurance policy for AMD in the event that TSMC's mass production of its N3 nodes were to face delays, significant wafer defect issues, or capacity issues. One industry analyst estimated early N3 wafer yields to be at 55% while others estimated yields to be similar to those of N5 at between 60-80%.[13][14] Additionally, Apple, as TSMC's largest customer, gets priority access to the latest process nodes. In 2022, Apple was responsible for 23% of TSMC's $72 billion in total revenue.[15] After N3 began ramping at the end of 2022, Apple bought up the entirety of TSMC's early N3B wafer production capacity to fabricate their A17 and M3 SoCs.[16] Zen 5 desktop and server processors continue to use the N6 node for the I/O die fabrication.[17]

Zen 5 Core Complex Dies (CCDs) are fabricated on TSMC's N4X node which is intended to accommodate higher frequencies for high-performance computing (HPC) applications.[18] Zen 4-based mobile processors were fabricated on the N4P node which is targeted more toward power efficiency. N4X maintains IP compatibility with N4P and offers a 6% frequency gain over N4P at the same power but comes with the trade-off of moderate leakage.[19] Compared to the N5 node used to produce Zen 4 CCDs, N4X can enable up to 15% higher frequencies while running at 1.2V.[20]

The Zen 5 CCD, codenamed "Eldora",[1] has a die size of 70.6mm2, a 0.5% reduction in area from Zen 4's 71mm2 CCD while achieving a 28% increase in transistor density due to the N4X process node.[21] Zen 5's CCD contains 8.315 billion transistors compared to the Zen 4 CCD's 6.5 billion transistors.[22] One Zen 5 core is larger than one Zen 4 core, but the CCD has been reduced via shrinking the L3 cache. The monolithic die used by "Strix Point" mobile processors, fabricated on TSMC's lower power N4P node, measures 232.5mm2 in area.[21]

Front end

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Branch prediction

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Zen 5's changes to branch prediction are the most significant divergence from any previous Zen microarchitecture. The branch predictor in a core tries to predict the outcome when there are diverging code paths. Zen 5's branch predictor is able to operate two-ahead where it can predict up to two branches per clock cycle. Previous architectures were limited to one branch instruction per clock cycle, limiting the instruction-fetch throughput of branch-heavy programs.[23] Two-ahead branch predictors have been discussed in academic research dating back to André Seznec et al.'s 1996 paper "Multiple-block ahead branch predictors".[24] 28 years after it was first proposed in academic research, AMD's Zen 5 architecture became the first microarchitecture to fully implement two-ahead branch prediction. Increased data prefetching assists the branch predictor.

Execution engines

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Integer units

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Zen 5 contains six Arithmetic Logic Units (ALUs), up from four ALUs in prior Zen architectures. A greater number of ALUs that handle common integer operations can increase per-cycle scalar integer throughput by 50%.[25]

Vector engines and instructions

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The vector engine in Zen 5 features four floating-point pipes compared to three pipes in Zen 4. Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling of the floating-point pipe width to a native 512-bit floating-point datapath. The AVX-512 datapath is configurable depending on the product. Ryzen 9000 series desktop processors and EPYC 9005 server processors feature the full 512-bit datapath, but Ryzen AI 300 mobile processors feature a 256-bit datapath in order to reduce power consumption. AVX-512 instruction has been extended to VNNI/VEX instructions. Additionally, there is greater bfloat16 throughput, which is beneficial for AI workloads.

Cache

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L1

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The wider front end in the Zen 5 architecture necessitates larger caches and higher memory bandwidth in order to keep the cores fed with data. The L1 cache per core is increased from 64 KB to 80 KB per core. The L1 instruction cache remains the same at 32 KB but the L1 data cache is increased from 32 KB to 48 KB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating-point unit pipes has also been doubled. The L1 data cache's associativity has increased from 8-way to 12-way in order to accommodate its larger size.

L2

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The L2 cache remains at 1 MB but its associativity has increased from 8-way to 16-way. Zen 5 also has a doubled L2 cache bandwidth of 64 bytes per clock.

L3

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The L3 cache is filled from L2 cache victims and in-flight misses. Latency for accessing the L3 cache has been reduced by 3.5 cycles.[26] A Zen 5 Core Complex Die (CCD) contains 32 MB of L3 cache shared between the 8 cores. In Zen 5 3D V-Cache CCDs, a piece of silicon containing 64 MB of extra L3 cache is placed under the cores rather than on top like in prior generations for a total of 96 MB.[27] This allows for increased core frequency compared to previous generation 3D V-Cache implementations which were sensitive to higher voltages. The Zen 5-based Ryzen 7 9800X3D has a 500 MHz increased base frequency over the Zen 4-based Ryzen 7 7800X3D and allows overclocking for the first time.[28]

Ryzen AI 300 APUs, codenamed "Strix Point", features 24 MB of total L3 cache which is split into two separate cache arrays. 16 MB of dedicated L3 cache is shared by the 4 Zen 5 cores and 8 MB is shared by the 8 Zen 5c cores.[29] Zen 5c cores are not able to access the 16 MB L3 cache array and vice versa.[30]

Cache Zen 4 Zen 5
L1
Data 		Size 32 KB 48 KB
Associativity 8-way 12-way
Bandwidth 32B/clk 64B/clk
L1
Instructions 		Size 32 KB 32 KB
Associativity 8-way 8-way
Bandwidth 64B/clk 64B/clk
L2 Size 1 MB 1 MB
Associativity 8-way 16-way
Bandwidth 32B/clk 64B/clk
L3 Size 32 MB 32 MB
Associativity 16-way 16-way
Bandwidth 32B/clk Read
16B/clk Write 		32B/clk Read
16B/clk Write

Other changes

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Other features and changes in the Zen 5 architecture, compared to Zen 4, include:

  • Memory speeds up to DDR5-5600 (From DDR5-5200) and LPDDR5X-7500 are officially supported.[31]
Zen 4 vs Zen 5 capabilities[32]
Attribute Zen 4 Zen 5
L1/L2 BTB 1.5K/7K 16K/8K
Return Address Stack 32 52
ITLB L1/L2 64/512 64/2048
Fetched/Decoded Instruction Bytes/cycle 32 64
Op Cache associativity 12-way 16-way
Op Cache bandwidth 9 macro-ops 12 inst or fused inst
Dispatch bandwidth (macro-ops/cycle) 6 8
AGU Scheduler 3x24 ALU/AGU 56
ALU Scheduler 1x24 ALU 88
ALU/AGU 4/3 6/4
Int PRF (red/flag) 224/126 240/192
Vector Reg 192 384
FP Pre-Sched Queue 64 96
FP Scheduler 2x32 3x38
FP Pipes 3 4
Vector Width 256 256b/512b
ROB/Retire Queue 320 448
LS Mem Pipes support Load/Store 3/1 4/2
DTLB L1/L2 72/3072 96/4096

Products

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Desktop

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Granite Ridge

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AMD announced an initial lineup of four models of Ryzen 9000 processors on June 3, 2024, including one Ryzen 5, one Ryzen 7 and two Ryzen 9 models. Manufactured on a 4 nm process, the processors feature between 6 and 16 cores.[33] Ryzen 9000 processors were released in August 2024.

In May 2025 four of these processors were also released in the 4005 range of the EPYC brand,[34] with the 4585PX corresponding to the 9950X3D, the 4565P to the 9950X, the 4345P to the 9700X, and the 4245P to the 9600. Two EPYC 4005 parts, both 65W, have no direct Ryzen 9000 series equivalent: the EPYC 4465P with 12 cores at 3.4 GHz, and the 4545P with sixteen cores at 3.0 GHz.

Common features of Ryzen 9000 desktop CPUs:

  • Socket: AM5.
  • All the CPUs support DDR5-5600 in dual-channel mode.
  • All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
  • Includes integrated RDNA2 GPU with 2 CUs and base and boost clock speeds of 0.4 GHz and 2.2 GHz, respectively. Models with "F" suffixes are without iGPUs.
  • L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
  • L2 cache: 1 MB per core.
  • Fabrication process: TSMC N4X FinFET (N6 FinFET for the I/O die).
Branding and Model Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		Thermal
solution 		TDP Chiplets Core
config[i] 		Release
date 		Launch MSRP
Base Boost
Ryzen 9 9950X3D[35][36] 16 (32) 4.3 5.7 128 MB[ii] — 170 W 2 × CCD
1 × I/OD 		2 × 8 March 12, 2025 US $699
9950X[38][39] 4.3 5.7 64 MB August 15, 2024 US $649
9900X3D[35][36] 12 (24) 4.4 5.5 128 MB[ii] 120 W 2 × 6 March 12, 2025 US $599
9900X[38][39] 4.4 5.6 64 MB August 15, 2024 US $499
Ryzen 7 9800X3D[40][41] 8 (16) 4.7 5.2 96 MB 1 × CCD
1 × I/OD 		1 × 8 November 7, 2024 US $479
9700X[38][39] 3.8 5.5 32 MB 65 W[iii] August 8, 2024 US $359
9700F[42] 65 W September 16, 2025 TBA
Ryzen 5 9600X[38][39] 6 (12) 3.9 5.4 65 W[iii] 1 × 6 August 8, 2024 US $279
9600[43] 3.8 5.2 Wraith Stealth 65 W February 19, 2025 TBA
9500F[44] 5.0 September 16, 2025 CN ¥1,299
  1. ^ Core Complexes (CCX) × cores per CCX
  2. ^ a b Only one of the two CCXes has 3D V-Cache.[37]
  3. ^ a b TDP configurable to 105 W

Shimada Peak

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AMD announced the Threadripper 9000 series of high-end desktop processors at Computex 2025, which released on July 30, 2025. These processors succeed the Zen 4 "Storm Peak" lineup and feature up to 96 Zen 5 cores. The processors come in two variants—the consumer "Threadripper" models and the more expensive workstation "Threadripper PRO" variants, which support more memory channels and PCIe lanes.[45]

Common features of Ryzen 9000 HEDT/workstation CPUs:

  • Socket: sTR5.
  • Threadripper CPUs support DDR5-6400 in quad-channel mode while Threadripper PRO CPUs support DDR5-6400 in octa-channel mode with ECC support.
  • L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
  • L2 cache: 1 MB per core.
  • Threadripper CPUs support 80 PCIe 5.0 lanes (4 of which runs PCIe 4.0 mode to the chipset; and remaining are usually running as 48 PCIe 5.0 lanes plus 24 PCIe 4.0 lanes), while Threadripper PRO CPUs support 128 PCIe 5.0 lanes (4 of which runs in PCIe 4.0 mode to the chipset), and extra 8 PCIe 3.0 lanes. Some lanes support alternative mode of running SATA3.
  • No integrated graphics.
  • Fabrication process: TSMC 4nm FinFET.
Branding and model Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[i] 		Release
date 		MSRP
Base Boost
Ryzen
Threadripper
PRO 		9995WX 96 (192) 2.5 5.4 384 MB 350 W 12 × CCD
1 × I/OD 		12 × 8 July 2025 [46] $11,699
9985WX 64 (128) 3.2 256 MB 8 × CCD
1 × I/OD 		8 × 8 $7,999
9975WX 32 (64) 4.0 128 MB 4 × CCD
1 × I/OD 		4 × 8 $4,099
9965WX 24 (48) 4.2 4 × 6 $2,899
9955WX 16 (32) 4.5 64 MB 2 × CCD
1 × I/OD 		2 × 8 $1,649
9945WX 12 (24) 4.7 2 × 6 TBA
Ryzen
Threadripper 		9980X 64 (128) 3.2 256 MB 8 × CCD
1 × I/OD 		8 × 8 $4,999
9970X 32 (64) 4.0 128 MB 4 × CCD
1 × I/OD 		4 × 8 $2,499
9960X 24 (48) 4.2 4 × 6 $1,499
  1. ^ Core Complexes (CCXs) × cores per CCX

Threadripper 9000 processors officially support up to 6400 MT/s DDR5 memory, a significant increase from 5200 MT/s in the previous generation.[47]

Mobile

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Strix Point & Krackan Point

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The Ryzen AI 300 series of notebook processors was announced on June 3, 2024. Codenamed Strix Point (for the high performance Ryzen AI 9 300 series) & Krackan Point (for the mid-range Ryzen AI 5 and 7 300 series), these processors are named under a new model numbering system similar to Intel's Core and Core Ultra model numbering. Strix Point features a 3rd-gen Ryzen AI engine based on XDNA 2, providing up to 50 TOPS of neural processing unit performance. The integrated graphics is upgraded to RDNA 3.5, and top-end models have 16 CUs of GPU and 12 cores of CPU, an increase from the maximum of 8 CPU cores on previous-generation Ryzen ultra-thin mobile processors.[48] Notebooks featuring Ryzen AI 300 series processors were released on July 17, 2024.[49]

Common features of Ryzen AI 300 notebook APUs:

  • Socket: BGA, FP8 package type.
  • All models support DDR5-5600 or LPDDR5X-8000 in dual-channel mode.
  • All models support 16 PCIe 4.0 lanes.
  • Native USB4 (40Gbps) Ports: 2
  • Native USB 3.2 Gen 2 (10Gbps) Ports: 2
  • iGPU uses the RDNA 3.5 microarchitecture.
  • NPU uses the XDNA 2 AI Engine (Ryzen AI).
  • Both Zen 5 and Zen 5c cores support AVX-512 using a half-width 256-bit FPU.
  • L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
  • L2 cache: 1 MB per core.
  • Fabrication process: TSMC N4P FinFET.
Branding and model CPU GPU NPU
(Ryzen AI) 		TDP Release
date
Cores (threads) Clock (GHz) L3 cache
(total) 		Model Clock
(GHz)
Total Zen 5 Zen 5c Base Boost
(Zen 5) 		Boost
(Zen 5c)
Ryzen AI 9 (PRO)
HX 375 		12 (24) 4 (8) 8 (16) 2.0 5.1 3.3 24 MB 890M
16 CUs 		2.9 55 TOPS 15–54 W June 2, 2024 [50]
(PRO)
HX 370[51] 		50 TOPS
365[51] 10 (20) 6 (12) 5.0 880M
12 CUs
Ryzen AI 7 PRO 360[52][53] 8 (16) 3 (6) 5 (10) 16 MB October 10, 2024 [54]
(PRO)
350 		4 (8) 4 (8) 3.5 860M
8 CU 		3.0 Q1 2025[55]
Ryzen AI 5 (PRO)
340 		6 (12) 3 (6) 3 (6) 4.8 3.4 840M
4 CU 		2.9
330 4 (8) 1 (2) 4.5 8 MB 820M
2 CU 		2.8 15–28 W July 2025 [56]

Strix Halo

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Strix Halo represented a major departure of previous multi-chiplet mobile processors. Strix Halo's CCD is actually not the same type of CCD used on regular Zen 5 desktop processors. Instead it features a unique "sea of wires" interconnect that replaces the previous infinity fabric. This change allowed for greater power efficiency but also greater design complexity. This type of interconnect is rumored to be on Zen 6, the next generation of AMD CPU microarchitecture.[57][58]

Common features of Strix Halo mobile CPUs:[59]

  • Socket: BGA, FP 11 package type.
  • All CPUs only support soldered LPDDR5X memory with a 256-bit memory bus.
  • All CPUs support 16 lanes of PCIe 4.0 lanes.
  • iGPU uses the RDNA 3.5 architecture.
  • Fabrication process: TSMC N4P FinFET.
Branding and Model CPU GPU NPU
(Ryzen AI) 		Chiplets Core config TDP Release date
Cores (threads) Clock (GHz) L3 cache
(total) 		Model Clock
(GHz)
Base Boost
Ryzen AI MAX+ (PRO)
395 		16 (32) 3.0 5.1 64 MB 8060S
40 CUs 		2.9 50 TOPS 2 × CCD
1 × I/OD with GPU 		2 × 8 45–120 W Q1 2025 [60]
Ryzen AI MAX (PRO)
390 		12 (24) 3.2 5.0 8050S
32 CUs 		2.8 2 × 6
(PRO)
385 		8 (16) 3.6 32 MB 1 × CCD
1 × I/OD with GPU 		1 × 8
PRO 380 6 (12) 3.6 4.9 16 MB 8040S
16 CUs 		1 × 6

Fire Range

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Common features of Ryzen 9000 Fire Range series:

  • Socket: FL1.
  • All models support dual-channel DDR5-5600 with a maximum capacity of 96 GB.
  • All models support 28 PCIe 5.0 lanes.
  • Native USB 3.2 Gen 2 (10 Gbps): 4.
  • Native USB 2.0 (480 Mbps): 1.
  • iGPU: AMD Radeon 610M (2 CU @ 2200 MHz).
  • No NPU.
  • Fabrication process: TSMC N4 FinFET (CCD) + TSMC N6 FinFET (I/OD).
Branding and Model Cores (threads) Clock (GHz) L3 cache
(total) 		Chiplets Core config TDP Release date
Base Boost
Ryzen 9 9955HX3D[61] 16 (32) 2.3 5.4 128 MB 2 × CCD
1 × I/OD 		2 × 8 54 W 1H 2025
9955HX[61] 16 (32) 2.5 64 MB
9850HX[61] 12 (24) 3.0 5.2 2 × 6

Server

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Turin

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Alongside Granite Ridge desktop and Strix Point mobile processors, the Epyc 9005 series of high-performance server processors, codenamed Turin, were also announced at Computex on June 3, 2024. It uses the same SP5 socket as the previous Epyc 9004 series processors, and will pack up to 128 cores and 256 threads on the top-end model. Turin will be built on a TSMC 4 nm process.[62]

Common features of EPYC 9000 server processors:

Branding and Model Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[i] 		Release
date 		Launch
price[a]
Base Boost
Epyc 9755 128 (256) 2.7 4.1 512 MB 500 W 16 × CCD
1 × I/OD 		16 × 8 October 10, 2024 US $12,984
9655P 96 (192) 2.6 4.5 384 MB 400 W 12 × CCD
1 × I/OD 		12 × 8 US $10,811
9655 US $11,852
9565 72 (144) 3.15 4.3 384 MB 400 W 12 × CCD
1 × I/OD 		12 × 6 US $10,486
9575F 64 (128) 3.3 5.0 256 MB 400 W 8 × CCD
1 × I/OD 		8 × 8 US $11,791
9555P 3.2 4.4 360 W US $7,983
9555 US $9,826
9535 2.4 4.3 300 W US $8,992
9475F 48 (96) 3.65 4.8 256 MB 400 W 8 × CCD
1 × I/OD 		8 × 6 US $7,592
9455P 3.15 4.4 192 MB 300 W 6 × CCD
1 × I/OD 		6 × 8 US $4,819
9455 US $5,412
9365 36 (72) 3.4 4.3 192 MB 300 W 6 × CCD
1 × I/OD 		6 × 6 US $4,341
9375F 32 (64) 3.8 4.8 256 MB 320 W 8 × CCD
1 × I/OD 		8 × 4 US $5,306
9355P 3.55 4.4 256 MB 280 W 8 × CCD
1 × I/OD 		8 × 4 US $2,998
9355 US $3,694
9335 3.0 4.4 128 MB 210 W 4 × CCD
1 × I/OD 		4 × 8 US $3,178
9275F 24 (48) 4.1 4.8 256 MB 320 W 8 × CCD
1 × I/OD 		8 × 3 US $3,439
9255 3.25 4.3 128 MB 200 W 4 × CCD
1 × I/OD 		4 × 6 US $2,495
9175F 16 (32) 4.2 5.0 512 MB 320 W 16 × CCD
1 × I/OD 		16 × 1 US $4,256
9135 3.65 4.3 64 MB 200 W 2 × CCD
1 × I/OD 		2 × 8 US $1,214
9115 2.6 4.1 125 W US $726
9015 8 (16) 3.6 4.1 64 MB 125 W 2 × CCD
1 × I/OD 		2 × 4 US $527
  1. ^ Manufacturer suggested retail price at launch
  1. ^ Core Complexes (CCX) × cores per CCX

Zen 5c

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Zen 5c ("Prometheus") is a compact variant of the Zen 5 ("Nirvana")[1] core, primarily targeted at hyperscale cloud compute server customers.[63] It will succeed the Zen 4c ("Dionysus") and Zen 4 ("Persephone") core.

Turin Dense
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A variant of Epyc 9005 using Zen 5c ("Prometheus") cores was also shown off at Computex. It will feature a maximum of 192 cores and 384 threads, and be manufactured on a 3 nm process.[62] Common features of EPYC Dense 9000 server processers:

Branding and Model Cores
(threads) 		Clock rate (GHz) L3 cache
(total) 		TDP Chiplets Core
config[i] 		Release
date 		Launch
price[a]
Base Boost
Epyc 9965 192 (384) 2.25 3.7 384 MB 500 W 12 × CCD
1 × I/OD 		12 × 16 October 10, 2024 US $14,813
9845 160 (320) 2.1 320 MB 390 W 10 × CCD
1 × I/OD 		10 × 16 US $13,564
9825 144 (288) 2.2 384 MB 12 × CCD
1 × I/OD 		12 × 12 US $13,006
9745 128 (256) 2.4 256 MB 400 W 8 × CCD
1 × I/OD 		8 × 16 US $12,141
9645 96 (192) 2.3 320 W 8 × 12 US $11,048
  1. ^ Manufacturer suggested retail price at launch
  1. ^ Core Complexes (CCX) × cores per CCX

See also

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  • Arrow Lake - a competing x86 CPU lineup from Intel for Granite Ridge, Fire Range, and the Ryzen AI 300 series
  • Lunar Lake - a competing mobile x86 CPU lineup for Ryzen AI 300 series
  • Granite Rapids - a competing x86 CPU lineup for Turin Classic
  • Sierra Forest - a competing x86 CPU lineup for Turin Dense

References

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  1. ^ a b c Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
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  14. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  15. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  16. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  17. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  18. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  19. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  20. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  21. ^ a b Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  22. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  23. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  24. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  25. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  26. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  27. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  28. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  29. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  30. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  31. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  32. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  33. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  34. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  35. ^ a b Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  36. ^ a b Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  37. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  38. ^ a b c d Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  39. ^ a b c d Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  40. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  41. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  42. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  43. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  44. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  45. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  46. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  47. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  48. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  49. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  50. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  51. ^ a b Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  52. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  53. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  54. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  55. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  56. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  57. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  58. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  59. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  60. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  61. ^ a b c Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  62. ^ a b Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
  63. ^ Lua error in Module:Citation/CS1/Configuration at line 2172: attempt to index field '?' (a nil value).
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